Substroke is a visual "language" for drawing dynamic pictures.
Scientific and societal progress hinges on people understanding information. Information is often best presented visually, with pictures. Pictures are best drawn visually, with an artist painting directly onto a canvas. But currently, dynamic pictures are created in code -- indirectly and non-visually. This is like painting over the telephone.
My goal is to let artists and researchers create information visualizations from scratch, using standard drawing tools. I hope to make data-dependent graphics almost as easy to draw as conventional static graphics.
The ubiquity of frustrating, unhelpful software interfaces has motivated decades of research into "Human-Computer Interaction." In this paper, I suggest that this long-standing focus on "interaction" may be misguided. For a majority subset of software, called "information software," I argue that interactivity is actually a curse for users and a crutch for designers, and users' goals can be better satisfied through other means.
Information software design can be seen as the design of context-sensitive information graphics. I demonstrate the crucial role of information graphic design, and present three approaches to context-sensitivity, of which interactivity is the last resort. After discussing the cultural changes necessary for these design ideas to take root, I address their implementation. I outline a tool which may allow designers to create data-dependent graphics with no engineering assistance, and also outline a platform which may allow an unprecedented level of implicit context-sharing between independent programs. I conclude by asserting that the principles of information software design will become critical as technology improves.
Although this paper presents a number of concrete design and engineering ideas, the larger intent is to introduce a "unified theory" of information software design, and provide inspiration and direction for progressive designers who suspect that the world of software isn't as flat as they've been told.
Download ICCAD paper: Bus Encoding To Prevent Crosstalk Delay
Download Masters thesis: Bus Encoding To Prevent Crosstalk Delay
A major problem in modern integrated circuit design is crosstalk delay. A falling voltage next to a rising voltage... ...fight each other through cross - coupled capacitance. The slow output transitions cause communication delay. On long buses , this delay can cripple the overall circuit speed. Existing solutions resorted to fragile and power-wasteful circuit tricks.
I invented self-shielding codes. These encode data on the bus such that crosstalk delay is eliminated. Encoder ensures that adjacent signals cannot make opposite transitions. No fighting on the bus! This solution uses logic, not analog tricks. It is efficient, portable, and provably correct.
In my thesis, I rigorously derive the theory behind these codes, and prove their fundamental performance limits and characteristics.
My paper has apparently inspired a lot of derivative work. I haven't really followed it. I was unhappy making chips go faster. Chips are already obscenely fast. Yet, computerized applications are stupider and more frustrating than ever. this cognitive dissonance drove me out of grad school, and eventually brought me to interface design.
Software PLA efficiently evaluates complex boolean expressions. Switch encoding transforms if/else chains into switch statements. Control optimization by logic network simplification radically transforms if/else structures.
Boolean expression to evaluate: Construct a bitmap table. Evaluate minterms in parallel. Initial control structure: (X, Y, Z are complex expressions) Final control structure: The index is calculated like a state encoding. Decompose control flow into a logic network. Minimize. Reconstruct software.
Modern datapaths are 32 bits wide. But many applications deal with narrower data. Can a processor architecture exploit this to save power?
short int audioSample = a + b; int sum = a + b; Savings Pipeline Clock Shifter Register File I-Decode 34% ALU Power Block Total savings in core
Sigma-deltas are (or used to be) rare in wireless applications. the low oversampling ratio is difficult to design for. This modulator achieves 10 bits at 20 Ms/s, using a 4th-order 2-1-1 cascade and 16x oversampling.